1. Field of the Invention
The present invention relates to a time base correction circuit, and more particularly to a clock generator thereof.
2. Related Background Art
A time base correction (TBC) circuit has been known in the art.
It generates a clock which follows a jitter included in an input video signal by a clock generator, samples the input video signal by the clock, writes the resulting digitized data to a memory, reads the data by a stabilized clock and converts it to an analog signal to produce a jitter-free input video signal.
A configuration of a conventional time base correction circuit is shown in FIG. 1.
In FIG. 1, numeral 1 denotes an input terminal. When a video signal including a jitter is applied from the input terminal 1 to a sync. signal separator 2, a horizontal sync. signal, a vertical sync. signal and a burst signal included in the video signal are separated by a sync. signal separator, and the horizontal sync. signal Hsync is applied to a phase sync. circuit (phase locked loop PLL) 3, the vertical sync. signal Vsync is applied to a write address generator 4, and the burst signal Bu is applied to a first phase comparator 5.
The phase sync. circuit 3 comprises a second phase comparator 6 for comparing phases of a feedback clock to be described later and the horizontal sync. signal, a loop filter 7 for determining a response rate, a voltage controlled oscillator (VCO) 8 having an oscillator frequency thereof controlled in accordance with the output of the second phase comparator 6 and a 1/N frequency dividing counter (write address generator) 9, and it generates a clock having M times as high frequency as that of the burst signal, which is phase-locked to the horizontal sync. signal.
A phase difference (in one period .+-.180.degree. of the burst signal) between the clock generated by the phase sync. circuit 3 and 1/M frequency divided by a 1/M frequency dividing counter 10 and the burst signal is detected by the first phase comparator 5 and a phase shifter 11 shifts the phase thereof in accordance with the phase difference and the clock frequency to match the phase with that of the burst signal, so that the phase shifter 11 produces the clock having M times as high as that of the burst signal which is required for the A/D conversion. In this manner, the clock which follows the jitter included in the video signal is produced.
The count in the 1/N frequency dividing counter 9 indicates an address in one horizontal sync. period of the data derived by sampling the input video signal by the A/D converter 12, and the content thereof is sent to the write address generator 4. The write address generator 4 generates an address to write into the memory 13 based on the vertical sync. signal produced by the sync. signal separation circuit 2 and the signal from the 1/N frequency dividing counter 9.
The output data of the A/D converter 12 is written at the above address in synchronism with the clock from the phase shifter 11 so that data corresponding to the time base is written into the memory 13 and the data written in the memory 13 is read by a stabilized clock (not shown). This data is sent to an output terminal 14 and it is converted to an analog signal by a D/A converter (not shown) to produce a jitter free video signal.
In the prior art time base correction circuit, however, when a time-compressed or time-expanded video signal is applied by fast feed or rewind operation of a video tape recorder (VTR), a normal image can be reproduced within a phase lock range of the phase sync. circuit 3, but beyond the lock range the image is so disturbed that the content thereof cannot be recognized.
Further, in the prior art time base correction circuit, when the video signal input is interrupted by some reason (for example, dropout generated in the reproduction by a VTR or laser disk), the sync. signal separation circuit 2 cannot produce the sync. signal and the phase sync. circuit 3 which is to generate the clock having the same frequency as that of the signal phase-locked to the horizontal sync. signal is disturbed.
In the recovery of the video signal input, the count of the 1/N frequency dividing counter 9 is disturbed and the phase sync. circuit 3 takes a long time to lock the phase.
As result, when the input video signal is interrupted and recovered, the clock signal output is unstable and the image is significantly disturbed.